1. Field of Invention
The present invention relates to an analog-to-digital (AD) conversion circuit and a solid-state imaging apparatus having the same.
2. Description of Related Art
As an example of an AD conversion circuit according to the related art, a configuration shown in FIG. 14 is well known (for example, see Takayuki Toyama et al., “A 17.7 Mpixel 120 fps CMOS Image Sensor with 34.8 Gb/s Readout,” Sony, Kanagawa, Japan ISSCC2011/SESSION23/IMAGE SENSORS/23.11). First, the configuration and operation of the AD conversion circuit of FIG. 14 will be described.
FIG. 14 shows a configuration of a single-slope AD conversion circuit according to the related art. The AD conversion circuit shown in FIG. 14 includes a first count section 1018, a second count section 1101, a latch section 1108, a comparison section 1109, and a buffer circuit BUF.
The first count section 1018 counts a clock signal CLK having a predetermined frequency as a count clock, and outputs binary count values D0 to D4. The comparison section 1109 has a voltage comparator COMP into which an analog signal Signal and a ramp wave Ramp are input. The analog signal Signal serves as an AD conversion target. The ramp wave Ramp decreases with the passage of time. The comparison section 1109 outputs a comparison output CO based on a result obtained by comparing the analog signal Signal to the ramp wave Ramp. In the comparison section 1109, a time interval (the magnitude of a time axis direction) corresponding to the analog signal Signal is generated.
The latch section 1108 latches logical states of the count values D0 to D4 output from the first count section 1018. In this example, the latch section 1108 includes latch circuits D_0 to D_4 of 5 bits. The count values D0 to D4 are input from the first count section 1018 to the latch circuits D_0 to D_4. The second count section 1101 counts an output Q4 of the latch circuit D_4 to which the count value D4 corresponding to a most significant bit (MSB) among the count values D0 to D4 output from the first count section 1018 is input as a count clock. In this example, the second count section 1101 includes a 7-bit counter circuit (not illustrated). The buffer circuit BUF is an inverting buffer circuit that inverts an input signal and outputs the inverted signal. Herein, a configuration of the inverting buffer circuit is used in order to facilitate the understanding of embodiments of the present invention as will be described later.
FIG. 15 shows an operation of the AD conversion circuit shown in FIG. 14. Hereinafter, the operation of the AD conversion circuit according to the related art will be described.
First, after an input of the analog signal Signal to be subjected to AD conversion has been stabilized, the ramp wave Ramp, which decreases with the passage of time, the ramp wave Ramp is input to one input terminal of the comparator 1109. The comparator 1109 compares the ramp wave Ramp to the analog signal Signal. Meanwhile, the first count section 1018 counts the clock signal CLK, for example, in a count-up mode, and outputs the count values D0 to D4. In addition, the second count section 1101 counts the output Q4 of the latch circuit D_4 of the latch section 1108.
The comparison section 1109 compares the ramp wave Ramp to the analog signal Signal, and inverts the comparison output CO at a timing at which voltages of the ramp wave Ramp and the analog signal Signal have been approximately consistent (a first timing). After the comparison output CO has been buffered by the buffer circuit BUF, a latch signal Hold is output from the buffer circuit BUF (a second timing). On the basis of the latch signal Hold, the latch circuits D_0 to D_4 of the latch section 1108 are in a disable state, so that logical states corresponding to the count values D0 to D4 are latched in the latch circuits D_0 to D_4 of the latch section 1108. When the latch circuit D_4 of the latch section 1108 is stopped, the second count section 1101 latches count values D5 to D11 at that time. Thereby, digital data DOUT[11:0] corresponding to the analog signal Signal is obtained.
In the AD conversion circuit of the related art described above, because the latch circuits D_0 to D_3 constituting the latch section 1108 continuously operate during a period of a time interval, a value of current consumed by the latch section 1108 increases.
In the AD conversion circuit of the related art, the latch circuits D_0 to D_3 constituting the latch section 1108 constantly operate in a period from a start time of a comparison by the comparison section 1109 to the second timing. In general, because an output (particularly, a count value D0 of a least significant bit (LSB)) from the first count section 1018 has a high frequency, current consumed by the latch circuits D_0 to D_3 constituting the latch section 1108 is high.
Here, an imager used in a digital still camera (DSC) or the like is considered as a specific example using the AD conversion circuit of the related art. Specifically, specs in which the number of pixels is 2000×104 and a frame rate is 120 frames/sec are assumed. Assuming that an AD conversion circuit is arranged for each column of a pixel array, a pixel array of 2000×104 pixels is designated as 4000 rows×5000 columns in length and width in order to facilitate description and a blanking period is absent for further simplicity, the number of rows from which pixel signals are read per second is as follows.120 frames/sec×4000 rows/frame=480K lines/sec
That is, a read rate of one row becomes 480 KHz. For example, for 10-bit resolution AD conversion, a count value is output from the first count section 1018 at a frequency of about 480 MHz, which is 1024 times greater than the read rate of one row. Further, for example, for 12-bit resolution AD conversion, a count value is output from the first count section 1018 at a frequency of about 2 GHz, which is 4096 times greater than the read rate of one row. In this case, assuming that a consumption current value of the latch circuits D_0 to D_3 constituting the latch section 1108 is 100 μA/column, a consumed current value for 5000 columns becomes as follows.100 μA/column×5000 columns=500 mA
Further, if the number of pixels, a frame rate, and resolution increase, a count value is output at a frequency of more than 2 GHz, which is a frequency estimated as described above, and the consumption current further increases.